Semiconductor memory devices have been continuously improved in terms of operating speeds and the degree of integration. In order to improve the operating speed, a synchronous memory device capable of operating in synchronization with a clock applied from outside the memory chip has been introduced in the art.
An SDR (single data rate) synchronous memory device inputs and outputs one data in one data pin in synchronization with the rising edge of a clock for one cycle of a clock applied from outside the memory device.
However, the SDR synchronous memory device is insufficient to satisfy the speed of a system requiring a high speed operation, and under this situation, a DDR (double data rate) synchronous memory device for processing two data for one cycle of a clock has been proposed.
In each data input/output pin of the DDR synchronous memory device, two data are consecutively inputted and outputted in synchronization with the rising edge and the falling edge of a clock inputted from an outside source. Therefore, because a band width at least two times wider than the SDR synchronous memory device may be realized without increasing the frequency of a clock, a high operation speed may be realized.
As the frequency of a clock increases for a high speed operation, it is important to secure a data valid window for testing data outputted from a semiconductor memory device.
FIG. 1 is a timing diagram for data outputted in synchronization with an internal clock in a conventional data output circuit.
Describing, with reference to FIG. 1, the data outputted in synchronization with an internal clock in the conventional data output circuit, a rising clock RCLK of the internal clock is generated by buffering a preliminary rising clock RCLKP generated in synchronization with the rising edge of an external clock CLK in an enable period of a first enable signal FOUTEN. A falling clock FCLK of the internal clock is generated by buffering a preliminary falling clock FCLKP generated in synchronization with the falling edge of the external clock CLK in the enable period of a second enable signal ROUTEN. That is to say, the rising clock RCLK and the falling clock FCLK are generated in synchronization with the rising edge and the falling edge of the external clock CLK in the periods in which the first and second enable signals FOUTEN and ROUTEN are enabled. Data are sequentially outputted through a DQ pad DQ in synchronization with the rising clock RCLK and the falling clock FCLK.
A first bit 0 of the data sequentially outputted through the DQ pad DQ is outputted to the DQ pad DQ during a period A with a time corresponding to one half cycle (0.5tCLK) of the external clock CLK. A second bit 1 of the data is outputted to the DQ pad DQ during a period B with a time corresponding to one half cycle (0.5tCLK) of the external clock CLK. That is to say, the bits of the data are sequentially outputted through the DQ pad DQ each bit for one half cycle (0.5tCLK) of the external clock CLK.
However, since a time for testing the levels of the data bits outputted to the DQ pad DQ should correspond to one half cycle (0.5tCLK) of the external clock CLK as in the period A and the period B, a valid window for testing the levels of the data bits is shortened as the external clock CLK is inputted with a high frequency, and thus, it is difficult to stably perform a data test.